Pat Gelsinger: Faster AI Chip Design Meets Physical Limits

Original source: Former Intel CEO: Why This is the Best Time to Build Hardware, published by a16z on 2026-10-09. Duration: 53:14.

Guest: Pat Gelsinger, former Intel and VMware CEO and a general partner at Playground Global. Hosts: Raghu Raghuram and Guido Appenzeller.

This article draws on the full video's English automatic captions, with identities and key technical context checked against company sources. Estimates and forecasts about manufacturing, industry scale and technology retain their speaker attribution. A mistaken reference to nuclear commissioning dates is corrected below.

A team might use AI to design a chip in 3 months, then spend another 9 months on fabrication, advanced packaging and rack integration before the system can begin doing useful work.

Pat Gelsinger uses that hypothetical to explain the gap between improving design tools and delivering usable computing capacity. A completed design still has a long journey ahead.

As chip design gets faster, the delays in manufacturing, moving data and supplying power become harder to ignore. His view of hardware opportunity spans that entire journey.

His perspective also reflects his career and investments. After decades in chips and infrastructure, Gelsinger now backs companies working on these problems. His Playground Global biography lists relationships with xLight, Ayar Labs and Snowcap Compute, among others. That context matters when assessing his preferences among competing technologies.

What AI can take over, through the lens of the 486

Gelsinger joined Intel at 18, later worked on the 386 and led architecture and design for the 486. He recalls a team that had to build its own hardware description language, compiler, placement, routing and timing tools to make the processor possible.

Better tools let engineers express objectives at a higher level instead of handling every detail themselves. He sees AI enabling a similar transition: a small group of experts guiding tools could perform digital logic design that previously demanded much more manual work.

Analog circuitry faces different constraints. SerDes, the circuitry responsible for high-speed signal transmission and reception, still depends heavily on measurements from real silicon. Without that feedback, designers may have to accept more conservative implementations.

Gelsinger also recalls testing Stanford classroom ideas against circuits at Intel and taking the resulting problems back to his professors. The recurring process connects theory, tools and working devices. AI can accelerate parts of it, while physical validation remains necessary. Original video: design tools and AI.

Why 3 months of design can leave 9 months of waiting

In Gelsinger's example, even a fast fabrication flow can take about 3 months, with advanced packaging adding roughly another 3 months. The chips must then become a rack-scale system.

He puts that subsequent physical implementation at approximately 9 months. Including production scale and software readiness, the path from starting a design to useful deployment could stretch to 1.5 years. These are illustrative estimates; a particular project depends on its process, supply chain and validation requirements.

That delay can change a product's value. A team optimizes for a particular model and execution pattern, only to ship after mainstream workloads have moved elsewhere. Gelsinger invokes Graphcore to illustrate how a technically defensible design can struggle to keep pace with changing applications.

He wants physical implementation to shrink to 1 or 2 months, supported by new lithography and cheaper prototyping flows. His example of fifty million dollars in mask costs underscores how upfront expense restricts experimentation. The shorter cycle is an ambition; the interview does not establish that it has been achieved.

Conservative design also leaves performance unused. Gelsinger criticizes current modeling of three-dimensional power behavior, hotspots and delivery, suggesting that guard bands can occupy about 40% of the power envelope. He supplies no test conditions for that figure. His point concerns headroom reserved against uncertainty, rather than a measured share of electricity wasted by every chip.

The next improvements need to shorten delivery of the complete system and reduce excessive margins left for unknowns. Original video: manufacturing, memory and power constraints.

How many AI chip architectures can survive?

The hosts describe a market with roughly 100 AI inference accelerators and ask whether cheaper development could support a more permanently diverse hardware landscape.

Gelsinger expects consolidation for three main reasons.

First, workloads keep changing. Hardware can be specialized for prefill, decoding or speculative execution today, while future reasoning, three-dimensional modeling, chemistry and biology demand a different balance of resources. Scientific computing may make 64-bit precision important again. An architecture optimized around one stage of today's workload may fit poorly in 2 to 4 years.

Second, deployment at scale remains expensive. Faster software development does not remove the need for racks, data centers, power commitments and supply chains. His rhetorical question about finding fifty billion dollars illustrates the scale of capital involved; it is not a disclosed project budget.

Third, major customers help select the platforms that grow. Hardware must evolve alongside models, software and applications. Sustained investment from important users is itself part of the competition.

Appenzeller makes the opposing case: AI can write optimized kernels and adaptation layers, reducing the historical cost of supporting multiple instruction sets, compilers and platforms. Workloads also differ in their demands for compute and memory bandwidth, leaving room for specialized designs.

Gelsinger allows for some heterogeneity but prefers platforms that absorb it internally behind a common interface. He also expects continuous learning to blur the distinction between training and inference, potentially changing the premises of specialized hardware. These are competing forecasts; the conversation does not establish that only one architecture can endure. Original video: specialization and consolidation.

Memory needs both technical progress and sustained investment

Gelsinger is sharply critical of high-bandwidth memory, or HBM, while acknowledging it as the best option currently available.

He points to bit density, the bandwidth available through interfaces along a chip's perimeter, and the power and thermal consequences of concentrating many devices together. Faster arithmetic delivers limited benefit if data cannot reach the compute engines in time.

He says he has personally been involved with at least 5 new memory architectures and knows of nearly 100 industry attempts. Optane is one example that failed to become a lasting mainstream replacement. His description of approximately 30 years dominated by DRAM, SRAM and flash concerns the difficulty of commercializing a new dominant memory technology. It should not erase progress within existing memory families.

His optimism rests on a change in demand and financing. He describes the industry's historical volatility as making money in only 1 year out of 5, making sustained research difficult. A host says the three largest vendors now rank among the world's top 20 companies by market value; Gelsinger estimates that industry value rose by $2.5 trillion over about 4 years. Neither provides a defined comparison set or observation dates. These remain informal interview estimates, not verified rankings or valuation data.

Technically, he is interested in ferroelectric materials, non-capacitive memories, and structures combining density, performance and stackability. He also discloses a recent investment in an unnamed memory startup still operating in stealth.

He is more cautious about flash or MRAM for these high-performance uses, citing limits in the underlying storage cell's speed. That is his technology preference; the interview provides no common test that rules out competing approaches.

AI makes memory performance central to system value and creates a stronger demand case for research that has struggled to attract sustained funding. Original video: HBM and new memory.

Taller stacks have to work thermally, electrically and economically

Bringing memory closer to compute reduces data movement. Stacking devices also makes every layer's defects, connections, power needs and heat affect the complete assembly.

Gelsinger resists treating 16 or 32 layers as a universal answer. He first discusses modest stacks of 3 to 5 layers, then makes a more specific argument that 2 to 4 memory layers near compute may offer a better balance of speed and manufacturability.

Those numbers need their context. Adding compute, power delivery and signal redistribution can already bring his proposed integrated assembly to about 8 layers. He is discussing a multifunction system tradeoff, not establishing a universal HBM layer limit. SK hynix's published technical account already discusses developing 16-layer HBM with advanced packaging.

Redundant cells can compensate for some defects, Gelsinger observes, but cannot repair a physically cracked die. As more value accumulates in a stack, a failure in any layer becomes more expensive.

Power must reach the interior, heat must escape, and optical connectivity may enter the package too. Voltage regulation, liquid cooling and heat-spreading materials consequently become parts of the same design problem. His joke about engineers becoming plumbers captures the need to design silicon, mechanics, power and cooling together. Original video: stacking and thermal management.

Bring optical links inward, while keeping memory close

Gelsinger favors moving more system input and output to optical connections, but dislikes moving core memory far from compute and accessing it through optical links.

Optical-electrical conversion and transmission still consume energy. He describes communication as potentially about 1,000 times more energy-intensive than computation, without specifying common distances, processes or arithmetic operations. The defensible takeaway is that moving data is expensive; the ratio is not a universal system constant.

He is also skeptical of processing in memory. Pushing selected operations into memory can require workloads to fit particular structures, limiting flexibility as applications evolve. He explicitly allows that better tools and new designs could change his assessment.

Interconnects between systems present a different tradeoff. He suggests that maintaining a 5-meter copper link can be harder and more expensive than a 100-meter optical link, and expects wider adoption of near-packaged or co-packaged optics in 2028 or 2029. That timing remains his forecast, dependent on laser supply, packaging, thermal stability and production scale.

Network organization may change as well. General-purpose networks handle unpredictable packet destinations; many large AI jobs produce substantial, more predictable flows. Gelsinger therefore sees an opportunity for optical circuit switching, with the boundary between scale-up and scale-out gradually becoming less distinct.

That argument applies to suitable AI clusters. It does not establish that packet switching throughout the internet will disappear. Original video: data movement and optical networks.

Electricity determines when the racks can turn on

Gelsinger argues that energy capacity constrains economic capacity in an AI-intensive economy. Land, racks and GPUs alone do not guarantee a data center can start operating on schedule.

He describes a roughly 10 to 15-year period of limited US electricity capacity growth, estimates recent growth around 4%, and suggests gas turbine lead times can reach 8 years. The interview supplies no complete data series, equipment specifications or measurement scope. Those figures cannot replace a project's power assessment, nor do they establish that the US economy stopped growing over that period.

His central concern is straightforward: even a million purchased GPUs cannot do useful work if promised electricity fails to arrive. He expects more projects to encounter default risk as a result. This is a warning about exposure, not evidence that a particular project has already defaulted.

One historical reference needs correction. Gelsinger says the last new US nuclear reactor came online about 20 years ago. Georgia Power's official announcement records commercial operation of Vogtle Unit 3 on 2023-07-31 and Unit 4 on 2024-04-29. The case for more dependable generation can be discussed alongside the correct commissioning record.

More supply is only part of the problem. Electricity also needs to reach chips efficiently. Gelsinger favors 800 V direct-current distribution with fewer intermediate conversions and is enthusiastic about vertical gallium nitride devices. He describes the possibility of converting 800 V directly to 48 V, 12 V or even 5 V, alongside improvements to solid-state transformers, switches and cooling.

NVIDIA's official explanation of 800 VDC likewise emphasizes reducing conversion stages and delivering more usable power to racks. It supports the direction without establishing the maturity of every device discussed in the interview.

Gelsinger also claims inadequate improvement in energy per floating-point operation across NVIDIA's last 5 chip generations. Without precision, workload or baseline definitions, that is not a reproducible cross-generation benchmark. He hopes new devices can change efficiency more fundamentally, citing his involvement with Snowcap Compute and the possibility of roughly 1,000-fold better power-performance from superconducting computing.

That multiple is his forward-looking assessment of an investee's technology. The interview contains no independent whole-system measurement including refrigeration overhead. Improved power conversion and breakthroughs in computing devices each need their own validation. Original video: energy, power delivery and new devices.

Agents need execution environments, and people need control

The conversation ends with familiar territory for the former VMware CEO: what should virtualization manage when agents increasingly run software?

Gelsinger names security boundaries, performance, migration, networking and storage. Abstractions built around operating systems and applications need to be reconsidered around a new kind of workload actor.

Appenzeller observes that agent-facing virtual machines also change the product. Agents may choose their own execution environments. Startup latency, interfaces and acceptable complexity differ from those of a person operating a console.

Gelsinger insists on retaining the human role. The execution layer should serve agents, while the management layer lets people set policies, impose constraints and observe system behavior. He invokes Dario Amodei's ideas about constitutions and guardrails to describe that need.

This is a direction for infrastructure development, not an announcement of a new product. Original video: virtualization for agents.

Read alongside the hardware discussion, it suggests a practical standard for evaluating innovation: does it increase computing capacity that can operate reliably over time? Faster design, shorter manufacturing cycles, better memory, power delivery and management tools all have to deliver against that standard.